Not Applicable.
Not Applicable.
The present specification relates generally to a process of forming a trench for an integrated circuit and, more particularly, to a dual damascene process of forming a trench for an integrated circuit (IC). Even more particularly, the present specification relates to a dual damascene process that uses a self-assembled monolayer.
The increased demand for higher performance integrated circuit (IC) devices has required the density of metallization lines to be increased and, in addition, has required the use of stacked layers to be increased. These requirements have necessitated the development of novel approaches in the methods of forming interconnections that not only integrate fine geometry definition but are also conducive to subsequent CMP (chemical mechanical polishing) processing. CMP is necessary to ensure that a subject layer is flat and planar enough to serve as a bottom layer for an additional layer.
As interconnection line widths shrink, the challenges of etching materials using photoresist-as-mask techniques have become increasingly difficult. A major cause of the difficulty is the large aspect ratios involved. The aspect ratio is the ratio of the depth of a feature being etched to the width of the feature (D/W) (or height-to-width in cross-section).
One method of forming a trench is a method known as a damascene process, which comprises forming a trench by masking and etching techniques and subsequent filling of the trench with the desired conductive material. The damascene process is a useful method for attaining the fine geometry metallization required for advanced semiconductor devices. A dual damascene process is a two-step sequential mask/etch process to form a two-level structure, such as a via, connected to a metal line above the via.
Conventional dual damascene processing technology entails depositing a triple layer sandwich consisting of a thick layer of an insulative material, an etch stop material having a high etch selectivity to the insulative layer, and a second thick layer of an insulative material. The two level structure is formed by masking and etching through the top layer of insulative material stopping on the layer of etch stop material, etching the etch stop material only, then performing a second masking and etching process in the top layer of insulative material only. The second mask and etch provides a larger trough than the first mask and etch with the second masking being an oversize masking.
The demand for increased density has required an increase in the aspect ratio of the photolithographic processes. However, the current dual damascene process has several problems that prevent the further increase of the aspect ratio. The lithography systems being used to expose the photoresist in the resist-as-mask process are limited by the wavelength of light used, the compositions of the photoresist, and the lithographic techniques employed.
Accordingly, an improved method of fabricating a trench on an integrated circuit is needed. Further, a method of fabricating a trench on an integrated circuit having a smaller width than available with conventional dual damascene processes is needed. Further still, what is needed is a method of fabricating a trench on an integrated circuit having a width which is controllable to dimensions not possible using conventional dual damascene processes. Further yet, what is needed is a method of forming interconnect lines for an IC using less critical masks than in conventional dual damascene processes. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to an exemplary embodiment, a method of fabricating a trench on an integrated circuit having first and second insulative layers includes: providing a layer of material over the insulative layers; forming a first self-assembled monolayer on the metal layer; etching the first self-assembled monolayer to form a first aperature in the layer of material; etching the first and second insulative layers through the first aperature to form a first portion of the trench; forming a second self-assembled monolayer on the layer of material; etching the second self-assembled monolayer to form a second aperature in the layer of material wider that the first aperature; and etching the second insulative layer through the second aperature to form a second portion of the trench.
According to another exemplary embodiment, a method of fabricating a trench and integrated circuit includes: providing an insulative material; providing a layer of material over the insulative material; providing etched selectivity to a portion of the layer by exposing the layer to a thiol; etching the portion having the etched selectivity to form a first aperature in the layer; etching the insulative material through the first aperature to form a first portion of the trench; and forming a second aperature wider than the first aperature and a second portion of the trench wider than the first portion of the trench.
According to yet another exemplary embodiment, an integrated circuit on a semiconductor substrate has first and second insulative layers. The insulative layers have different etched selectivities. Integrated circuit has a trench fabricated by the following process: providing a metal layer over the insulative layer; forming a first self-assembled monolayer on the metal layer; etching the first self-assembled monolayer to form a first aperature in the monolayer; etching the first and second insulative layers through the first aperature to form a first portion of a trench; forming a second self-assembled monolayer on the metal layer; etching the second self-assembled monolayer to form a second aperature in the metal layer wider than the first aperature; and etching the second insulative layer through the second aperature to form a second portion of a trench.